1. Field of the Invention
The present invention relates to a technology for driving a display device, and more particularly, to a driving control circuit of a display device that is capable of displaying data generated therein, when a data driving circuit having a timing controller merged with a source driver receives an abnormal display signal.
2. Description of the Related Art
In recent years, flat-panel display devices, such as a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting diode (OLED) panel and the like, have been widely used. Among such devices, liquid crystal displays are continually proliferating.
As a typical example of a flat panel display device, the liquid crystal display is configured to include a display panel (or a liquid crystal panel), in which a plurality of gate lines and a plurality of data lines are arranged in directions perpendicular to each other to create a pixel area having a matrix form; a driving circuit portion, for supplying driving signals and data to the display panel; and a backlight, for providing light to the display panel.
FIG. 1 shows a block diagram of a display device that includes a display panel and a driving circuit portion according to the related art. As shown in FIG. 1, the display device is configured to include a display panel 110, a timing controller 120, a plurality of source drivers 130A to 130C, and a gate driver 140.
Referring to FIG. 1, the display panel 110 includes a plurality of pixels arranged at intersections of the plurality of gate lines and the plurality of data lines in a matrix form. Each of the pixels includes a transistor and a display device, and the transistor transfers data inputted from the data line to the display device in response to a scan signal supplied from the corresponding gate line.
The timing controller 120 generates a gate control signal for controlling the gate driver 140 and data control signals for controlling the source drivers 130A to 130C by using vertical and horizontal sync signals and a clock signal supplied from a system. In addition, the timing controller 120 rearranges digital video data RGB (hereinafter, referred to as ‘data’) inputted from the system, and supplies the rearranged data to the source drivers 130A to 130C.
The source drivers 130A to 130C convert the data into a signal corresponding to a gray scale value and supply the signal to data lines of the display panel 110, in response to the data control signal supplied from the timing controller 120.
The gate driver 140 supplies a scan signal to the gate line in response to the gate control signal supplied from the timing controller 120, and drives horizontal lines of the display panel 110 to which the data are supplied.
In response to a state in which an abnormal display signal is inputted, the timing controller 120 provides data (mainly, black data) generated from an oscillator therein to the source drivers 130A to 130C. The state in which an abnormal display signal is inputted includes a first state in which power is supplied and a signal is not inputted or a second state in which a signal deviating from a normal operational range is inputted even though power is applied and a signal is inputted. The first state may include a state in which power is applied but a horizontal synchronization signal, a vertical synchronization signal, a data enable signal or a data clock is not inputted, and the second state may include a state in which a signal is inputted at a frequency of less than 20 Hz or more than 100 Hz, which deviates from a permissible range, when supposing that the frequency of a vertical synchronization signal for normal display is 60 Hz.
Even when an abnormal display signal is inputted, the timing controller 120 provides data for expressing a black screen to the source drivers 130A to 130C.
In recent years, in order to meet the needs of larger and thinner display devices, a product in which a timing controller is merged with a source driver has been developed. Hereafter, a source driver merged with a timing controller will be referred to as ‘TMIC’.
Thus, the TMIC includes an oscillator and performs a timing control function and a source driving function. Accordingly, when a plurality of TMICs is used for driving the display panel, deviation may occur between the frequencies generated from the oscillators included in the respective TMICs. Thus, data outputted from the respective TMICs may not be synchronized with each other. This is because each of the TMICs outputs data using the horizontal synchronization signal, the vertical synchronization signal, and the data enable signal, which are generated through the clock signal having a frequency deviation.
In addition, due to the frequency deviation between the clock signals generated through the oscillators of the respective TMICs, an enable interval of the data enable signal generated from the TMIC with the oscillator, which generates the clock signal having the slowest frequency, may become longer than one horizontal interval of the horizontal synchronization signal generated from the TMIC with the oscillator which generates the clock signal having the fastest frequency.
Further, due to the frequency deviation between the clock signals generated through the oscillators of the respective TMICs, the last data latch enable signal of each TMIC may precede a gate output enable signal of the gate driver. The above-described problem occurs due to the frequency deviation between the respective TMICs.
Accordingly, the display device of the related art has various problems in that data are not synchronized with each other due to the frequency deviation between the clock signals generated through the oscillators of the respective TMICs, and thus has difficulties in displaying a natural black screen on a display panel when an abnormal display signal is inputted.